1. Field of the Invention
The present invention relates to clock and data recovery systems and, more specifically, to integrator-based front ends and bang-bang phase detectors for clock and data recovery.
2. Description of the Related Art
High-speed (e.g., 2.5-3.125 Gb/s) serial links are commonly used for chip-to-chip interconnects in high-speed network systems. For example, synchronous optical network (SONET) OC-768 applications may utilize 16 channels of 2.5 GB/s to support full duplex I/O of 40 GB/s. Many high-speed communications systems use asynchronous communication, where data is transmitted without a separate clock signal. Since a separate clock signal is not used, at a receiver side of a communications system, clock recovery circuitry is employed to extract intrinsic clock information from incoming data signals. Once extracted, the recovered clock is then used to re-time and regenerate the data originally transmitted. Such a clock and data recovery (CDR) circuit typically includes a voltage-controlled oscillator, a phase-locked loop (PLL), and/or a delay-locked loop (DLL) circuit as part of the clock recovery circuit, as well as deserialization logic as part of the data recovery circuit. Various techniques are used within CDR systems. Many of these are discussed in Sidiropoulos, S., and Horowitz, M., “A Semidigital Dual Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 32, no. 11, November 1997, incorporated herein by reference.
Generally, CDR systems suffer from extreme sensitivity to clock skew between clock domains within the CDR circuit. This is because, in these systems, the goal is to generate recovered clock edges which are ideally located to allow registration of the incoming data at a point of maximum signal quality. Given the high-speed nature of these systems and the relatively low noise margin, even minor errors in the alignment of clock edges to data availability may result in erroneous data being captured. Managing this problem in the context of a typical GHz-rate deserializer requires extreme care to be used in matching of the clock paths and balancing of the clock distribution system. In a typical 10 GHz system, the allowable timing uncertainty when the system is set for maximum sensitivity can be as low as 5 ps. Alternatively, accepting a greater timing uncertainty reduces jitter tolerance due to degraded signal-to-noise ratio (SNR).